Design of Pulse Triggered Flip Flop Using Pulse Enhancement Scheme

For the past several years, much progress has been made in Low power VLSI Design .In This paper ,a novel low-power pulse Triggered flipflop design is presented. First, the pulse generation control logic an AND function, is removed from critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for saving. Various post layout simulation results based on UMC CMOS 90-nm technology reveal that the proposed design features the best power-delay-product performance in four FF designs under comparison.